FRISC-V chip
Three processor iterations in 130 nm, 65 nm and 28 nm technology, manufactured in European foundries, with accompanying software packages.
FERICA – FER Initiative for Chips and Architectures
FER Initiative for Chips and Architectures. We are designing FRISC-V, the first Croatian RISC-V processor.
01 — About
The first Croatian RISC-V processor
FERICA (FER Initiative for Chips and Architectures) is a research and development project of the Faculty of Electrical Engineering and Computing, University of Zagreb, focused on the design and implementation of the first Croatian processor based on the open RISC-V architecture: FRISC-V. The goal is to develop several iterations of the processor, manufacture them in European semiconductor foundries, and test and verify them thoroughly.
3FRISC-V chip iterations
130 / 65 / 28 nmprocess nodes
2025 – 2029project duration
RISC-Vopen architecture
Education
New generations of FER students learn processor and chip design, while FER builds up its competencies in digital chip design.
Openness
Contributions to the open-source RISC-V community, optimization of AI algorithms for RISC-V, and collaboration with industry.
02 — From idea to silicon
The complete processor lifecycle
The project covers every step of development and builds infrastructure for chip testing and verification.
- 01
Concept
Requirements and the initial processor idea.
- 02
Architecture
RISC-V core and system with peripherals.
- 03
Design
Design and verification of individual components.
- 04
Tapeout
Fabrication in European foundries.
- 05
Testing
Evaluation of the complete system on real silicon.
03 — FRISC-V
FRISC-V on IHP SG13CMOS5L
FRISC-V is a RISC-V processor developed at FER. The first tapeout targets IHP's 130 nm SG13CMOS5L process on a multi-project wafer (MPW) run. The entire RTL-to-GDSII flow uses open-source tools.
In simulation the chip boots an operating system to the login prompt, and the riscv-arch-test suite passes in full.
- ISA
- RV32IMA + S/U (Sv32 paging)
- Process
- IHP SG13CMOS5L, 130 nm
- Die
- 2.1 × 2.1 mm (4.41 mm²)
- Package
- QFN-64
- Clock
- 80 MHz (sign-off, all three corners)
- Memory
- 8 KiB OCM / LLC, external HyperBus RAM
- Peripherals
- QSPI (flash + SD), UART, JTAG debug, GPIO
- Tools
- Yosys, OpenROAD, LibreLane, KLayout
- Roadmap
- 3 chip iterations: 130 nm, 65 nm and 28 nm
04 — Papers
Publications
Streamlined RISC-V Processor Tapeout with Open-Source Electronic Design Automation and Multi-Project Wafer Services
The paper presents a methodology for academic RISC-V processor tapeout using open-source EDA tools and multi-project wafer services. It compares the open-source Yosys / OpenROAD / OpenLane flow with commercial alternatives and surveys European tapeout access routes such as Europractice and the open IHP SG13G2 PDK. The central design case is FRISC-V.
Using Simulation for Teaching Computer Architecture in Higher Education
05 — Team
The people behind ferica
The project brings together FER researchers, led by the HPC Architectures and Applications Research Center, with experience in European initiatives such as DARE, EPI, EUPEX and EUPILOT.
Principal investigator
Assoc. Prof. Daniel Hofman, Ph.D.
Associate Professor at the Department of Control and Computer Engineering, FER, and Vice-President of the HPC center. Research in many-core architectures, Network-on-Chip (NoC) and multimedia processing.
Team member
Prof. Mario Kovač, Ph.D.
Full Professor at FER and Director of the HPC center. Active in the European Processor Initiative and the EuroHPC Joint Undertaking.
Team member
Assoc. Prof. Josip Knezović, Ph.D.
Associate Professor at FER and Vice-President of the HPC center. Research in energy-efficient, high-performance and embedded computing systems.
Project researchers
Danko Basch
Hrvoje Mlinarić
Antonio Petošić
Vlado Sruk
Igor Čavrak
Luka Mrković
Josip Ramljak- Filip Horvat
Hana Ivandić- Ana Šikić
Emanuel Guberović- Branimir Malnar
Student collaborators
- Emil Popović
- Matej Jurasić
- Jan Kozina
- Dominik Damjanović
- Robert Vitaliani
- Šimun Čović
Funding
Funded by the European Union – NextGenerationEU, through the Recovery and Resilience Facility (call for institutional research projects, 2025).
European context
FERICA directly supports the goals of the EU Chips Act and the EuroHPC initiatives: digital sovereignty, processor design and a national RISC-V ecosystem.
06 — Contact
Join the effort
Anyone who wants to take part in the development and tapeout of the first Croatian RISC-V processor – students, researchers and industry – is welcome to get in touch.
